Programmable capacitors and methods of using the same

ABSTRACT

In a first aspect, a first method of adjusting capacitance of a semiconductor device is provided. The first method includes the steps of (1) providing a transistor including a dielectric material having a dielectric constant of about 3.9 to about 25, wherein the transistor is adapted to operate in a first mode to provide a capacitance and further adapted to operate in a second mode to change a threshold voltage of the transistor from an original threshold voltage to a changed threshold voltage such that the changed threshold voltage affects a capacitance provided by the transistor when operated in the first mode; and (2) employing the transistor in a circuit. Numerous other aspects are provided.

The present application is a continuation of and claims priority to U.S.patent application Ser. No. 11/353,516, filed Feb. 14, 2006, which ishereby incorporated by reference herein its entirety.

CROSS-REFERENCE TO RELATED APPLICATION

The present application is related to U.S. patent application Ser. No.11/353,493, filed Feb. 14, 2006 and titled “MEMORY ELEMENTS AND METHODSOF USING THE SAME” (Attorney Docket No. ROC920050313), which is herebyincorporated by reference herein in its entirety.

FIELD OF THE INVENTION

The present invention relates generally to semiconductor devices, andmore particularly to programmable capacitors and methods of using thesame.

BACKGROUND

A conventional transistor may be employed as a capacitor. A plurality ofsuch transistors may be coupled to form an array of capacitors. However,a large amount of circuitry and additional process complexity arerequired to maintain a state of the capacitor array. Further, such aconventional transistor may not provide low leakage (e.g., voltage orcapacitance leakage), a wide tuning range and be adapted to integrateeasily into existing complementary metal-oxide-semiconductor fieldeffect transistor (CMOS) processing. Accordingly, an improved capacitorand circuitry formed thereby, and methods of using the same are desired.

SUMMARY OF THE INVENTION

In a first aspect of the invention, a first method of adjustingcapacitance of a semiconductor device is provided. The first methodincludes the step of providing a transistor including a dielectricmaterial having a dielectric constant of about 3.9 to about 25. Thetransistor is adapted to operate in a first mode to provide acapacitance and further adapted to operate in a second mode to change athreshold voltage of the transistor from an original threshold voltageto a changed threshold voltage. The changed threshold voltage affects acapacitance provided by the transistor when operated in the first mode.The first method also includes the step of employing the transistor in acircuit.

In a second aspect of the invention, a first apparatus is provided. Thefirst apparatus is a semiconductor device having an adjustablecapacitance that includes a transistor formed on a substrate having agate region including a dielectric material having a dielectric constantof about 3.9 to about 25. The transistor is adapted to (1) operate in afirst mode to provide a capacitance; and (2) operate in a second mode tochange a threshold voltage of the transistor from an original thresholdvoltage to a changed threshold voltage such that the changed thresholdvoltage affects a capacitance provided by the transistor when operatedin the first mode.

In a third aspect of the invention, a first system is adapted to providea variable capacitance. The first system is a circuit that includes atleast one transistor including a dielectric material having a dielectricconstant of about 3.9 to about 25. Each transistor is adapted to operatein a first mode to provide a capacitance. Further, each transistor isadapted to operate in a second mode to change a threshold voltage of thetransistor from an original threshold voltage to a changed thresholdvoltage such that the changed threshold voltage affects a capacitanceprovided by the transistor when operated in the first mode. Acapacitance provided by the circuit is based on the capacitance providedby each transistor. Numerous other aspects are provided in accordancewith these and other aspects of the invention.

Other features and aspects of the present invention will become morefully apparent from the following detailed description, the appendedclaims and the accompanying drawings.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a graph illustrating a relationship between capacitance ratioand voltage.

FIG. 2 is a schematic diagram of a phase-locked loop (PLL) including aprogrammable capacitor in accordance with an embodiment of the presentinvention.

FIG. 3 is a schematic diagram of a first exemplary voltage-controlledoscillator (VCO) included in the PLL in accordance with an embodiment ofthe present invention.

FIG. 4 is a schematic diagram of a second exemplary VCO included in amodified version of the PLL in accordance with an embodiment of thepresent invention.

FIG. 5 is a schematic diagram of a capacitor array including at leastone programmable capacitor in accordance with an embodiment of thepresent invention.

DETAILED DESCRIPTION

The present invention provides an improved capacitor and circuitryformed thereby, and methods of using the same. More specifically, thepresent invention may employ a transistor including a dielectricmaterial having a dielectric constant of about 3.9 to about 25 as acapacitor. A threshold voltage of the transistor may be adjusted byapplying a bias voltage to a gate of the transistor. In this manner, acapacitance of the transistor may be adjusted, and the transistor may betuned to provide a desired capacitance. Such an adjustable capacitor maybe employed in a variety of circuits. For example, such a capacitor maybe used to adjust a frequency employed by a phase-locked loop (PLL).

Alternatively, in some embodiments, a plurality of such capacitors maybe employed in a binary-weighted array of capacitors. A capacitance ofsuch an array may be based on control signals (e.g., bits) asserted onone or more inputs of the array. For example, if a control signal isasserted on a first input of the array, a capacitance of the array maybe based on a first set of capacitors, which are coupled to the firstinput, included in the array. Alternatively, if a control signal isasserted on a second input of the array, the capacitance of the arraymay be based on a second set of capacitors, which are coupled to thesecond input, included in the array and so on. A capacitance of such anarray may further be based on programming signals coupled to the array.Such programming signals may be employed to adjust threshold voltages ofone or more transistors of the array, thereby affecting respectivecapacitances subsequently provided by such transistors, and thereforethe capacitance of the array. The control signals may serve as a coarseadjustment and the programming signals may serve as a fine adjustment ofcapacitance provided by the array, or vice versa.

In this manner, the present invention may provide a capacitor whosecapacitance may be varied and circuitry formed thereby, and methods ofusing the same.

FIG. 1 is a graph illustrating a relationship between capacitance ratioand voltage. A conventional metal-oxide-semiconductor field-effecttransistor (MOSFET) (e.g., which may be an n-channel MOSFET (NFET))formed on a substrate may be employed as a capacitor, which may providea capacitance C, by applying a voltage Vg to a gate of the MOSFET whilegrounding the substrate and a source and drain of the MOSFET. Withreference to FIG. 1, the graph 100 illustrates a relationship between acapacitance-to-gate dielectric capacitance per unit area ratio (C/Cox)and a voltage Vg applied to the MOSFET gate for a capacitor underdifferent conditions. For example, a first curve 102 of the graph 100illustrates the relationship between C/Cox and Vg for the MOSFET, asecond curve 104 of the graph 100 illustrates the relationship ifsource/drain diffusion regions are no longer present and a third curve106 of the graph 100 illustrates the relationship if the MOSFETundergoes deep depletion. The capacitance described by the curves 102,104, 106 is representative of a small signal measurement superimposedupon a transient or DC bias value.

Capacitance provided by the MOSFET depends on a gate-to-diffusion regionbias as follows. The first curve 102 may apply to MOSFETs employed inaccordance with an embodiment of the present invention. For example, thefirst curve 102 may illustrate low frequency operation in which anapproximately unlimited supply of minority carriers (e.g., electrons)may be available to a channel region of the MOSFET from the adjacentsource/drain diffusion regions of the MOSFET. Accumulation may refer toa condition in which depletion does not occur in a top surface of thesubstrate. Therefore, a top surface of silicon of the MOSFET is a P-typematerial. With reference to the first curve 102, while in accumulationwith a negative gate voltage Vg applied to the NFET, and the substrate,source and drain grounded, the NFET may provide a gate capacitance Cequal to the gate dielectric capacitance per unit area Cox. As shown,when the NFET, which is employed as a capacitor, is biased far enoughinto accumulation by application of negative gate bias Vg, a change inVt may not change the capacitance C provided by the NFET from Cox.

When the gate bias voltage Vg is 0, the NFET is at flat band andprovides a flat-band capacitance C_(fb). At flat band, a surfacepotential Ψ_(s) is 0. From this point, an increasingly positive gatebias voltage Vg may cause silicon depletion to expand, therebydecreasing capacitance provided by the NFET. As the capacitancedecreases while an increasingly positive gate bias voltage Vg is appliedto the NFET, the surface potential Ψ_(s) may equal Ψ_(B) which is thedifference between Fermi level and intrinsic level. Once maximumdepletion depth is reached, a minimum capacitance C_(min1) provided bythe NFET may be reached. From this point of the first curve 102, anincrease in gate bias voltage Vg may cause an inversion layer to form(e.g., quickly) from carriers in the source/drain diffusion regions ofthe NFET. Consequently, the capacitance C provided by the NFET mayincrease toward Cox. When the gate bias voltage is increased to athreshold voltage (Vt) of the NFET, Ψ_(s) may equal 2×Ψ_(B).

Alternatively, if source/drain diffusion regions are no longer present,in the absence of minority carrier generation, a capacitance (e.g.,steady state capacitance) provided by the NFET may follow the secondcurve 104 to reach a minimum capacitance C_(min2). While reachingC_(min2), as the gate bias voltage is increased to a Vt of the NFET,Ψ_(s) may equal 2×Ψ_(B). However, thermal generation of minoritycarriers may cause a surface of the silicon to be partially populatedwith an n-type material, thereby forming a weak inversion layer.Consequently, the capacitance provided by the NFET may increase slightly(from that shown in the second curve 104) as the gate bias voltage Vgincreases.

Alternatively, an abrupt increase in gate bias voltage Vg may cause theNFET to enter deep depletion. As illustrated by the third curve 106, thecapacitance provided by the NFET may decrease until a voltage at whichsemiconductor breakdown is reached. Alternatively, under deep depletionconditions, the capacitance provided by the NFET may at first decrease.However, thereafter, carrier generation may cause the capacitanceprovided by the NFET to increase to a steady state capacitance which isless than Cox.

The present invention employs a MOSFET (e.g., an NFET) including adielectric material having a high dielectric constant (hereinafterrepresented as “k” or “ε_(d)”), such as HfSiO and/or the like. Forexample, the MOSFET may include dielectric material having a k betweenabout that of SiO2 (e.g., 3.9) and about that of HfO2 (e.g., 25)depending on the exact chemical composition (although MOSFETs inaccordance with an embodiment of the present invention may includingdielectric material having a k within a larger or smaller and/ordifferent range). As described in U.S. patent application Ser. No.11/353,493, filed Feb. 14, 2006 and titled “MEMORY ELEMENTS AND METHODSOF USING THE SAME” (Attorney Docket No. ROC920050313), which is herebyincorporated by reference herein in its entirety, a MOSFET includingsuch a high-k dielectric material may operate in a first mode (e.g., afunctional mode) to store data and operate in a second mode (e.g., aprogramming mode) to change a Vt of the MOSFET from an original Vt to achanged Vt such that the changed Vt affects data stored by the memoryelement when operated in the first mode. For example, the MOSFET may beoperated in the second mode by applying a gate bias voltage of about+2.0 V or about +2.5 V for less than about 1 second. However, a largeror smaller and/or different gate bias voltage may be employed.Additionally, the gate bias voltage may be applied to the MOSFET for alonger or shorter time period. In this manner, an original Vt of theMOSFET may be adjusted to the changed Vt, which may be higher than theoriginal Vt without any other form of device degradation. The originalVt may be restored or nearly restored by application of a negative gatebias voltage (e.g., −2.0 V) for a time period (e.g., less than 1 second)without inducing device degradation. Consequently, the original Vt maybe recoverable. Additional details operating the MOSFET to store dataare described in U.S. patent application Ser. No. 11/353,493, filed Feb.14, 2006 and titled “MEMORY ELEMENTS AND METHODS OF USING THE SAME”(Attorney Docket No. ROC920050313), which is hereby incorporated byreference herein in its entirety, and therefore, are not described indetail herein.

Such a MOSFET formed on a substrate may provide a capacitance when abias voltage is applied to a gate of the MOSFET, and the substrate,source and drain of the MOSFET are grounded. The capacitance provided bythe MOSFET is based on the Vt thereof. Consequently, the MOSFET may beoperated in the first mode as a capacitor while having a first Vt (e.g.,the original Vt), thereby providing a first capacitance. Thereafter, theMOSFET may be operated in the second mode such that the Vt of the MOSFETis adjusted from the first Vt to a second Vt (e.g., a first changed Vt).Subsequently, the MOSFET may be operated in the first mode while havingthe second Vt, thereby providing a second capacitance. Additionally, theMOSFET may be operated in the second mode such that the Vt of the MOSFETis adjusted from the second Vt to a third Vt (e.g., a second changedVt), which may be equal to or approximately equal to the first Vt.Thereafter, the MOSFET may be operated in the first mode while havingthe third Vt, thereby providing a third capacitance which may beapproximately equal to the first capacitance.

For example, the MOSFET may be operated in the first mode as a capacitorwhile having the original Vt, thereby providing a first gate capacitanceCg1. To provide the first gate capacitance Cg1, a first voltage Vg1 maybe applied to the gate of the MOSFET. The first gate voltage Vg1 may beselected from the portion of the first curve 102 in which C/Cox declines(e.g., rapidly). For example, a gate bias voltage of about 0 V to abouta voltage at which C_(min1) is reached may be selected (although thegate bias voltage may be selected from a larger or smaller and ordifferent range). Because the selected gate bias voltage corresponds toa rapidly changing portion of the first curve 102, in some embodiments,a highly regulated power supply may be employed to provide Vg1, therebyreducing and/or eliminating variation of capacitance provided by theMOSFET. For a selected Vg1, a first gate capacitance Cg1 provided by theMOSFET may be determined using the following formula:

Cg1=Cox/{1+[2×Cox ² ×Vg1/(ε_(si) ×Q×N _(a))]}^(0.5),

where Cox is the capacitance/unit area for the high-k gate dielectric,ε_(si) is the dielectric constant for silicon, Q is charge of anelectron in Coulombs and N_(a) is acceptor impurity density in P-typesilicon. The capacitance/unit area may be determined using the followingformula:

Cox=ε _(o)×ε_(d) /tox,

where ε_(o) is the vacuum permittivity which is equal to 8.85×10¹⁴ F/cm,ε_(d) is the relative dielectric constant for the high-k dielectric andtox is a thickness of the high-k dielectric. Therefore, Cg1 mayrepresent an operational capacitance of the NFET before a Vt thereof ischanged. Therefore, a capacitance provided by a circuit comprising theMOSFET may be based on Cg1.

The MOSFET may be operated in second mode to change a Vt thereof. Forexample, a gate bias voltage or stress Vg2 of about +2.5 V may beapplied to the MOSFET for a time t1 of about less than 1 second to causea threshold voltage change ΔVt in the MOSFET. For example, the Vt may beincreased from the original Vt to the first changed Vt. Such a ΔVt mayshift the first curve 102 to the right. More specifically, a trappednegative charge in the gate dielectric of the MOSFET may cause +ΔVt,which may be mirrored as positive charge in a surface of silicon of theMOSFET. Consequently, after the threshold voltage change, a larger gatevoltage may be required to achieve a desired depletion level than thegate voltage required to obtain such depletion level before thethreshold voltage shift. Therefore, after inducing the ΔVt, when theMOSFET is operated in the first mode as a capacitor while having thefirst changed Vt, in response to the original gate bias voltage of Vg1,the MOSFET may provide a second gate capacitance Cg2 which may be largerthan the first gate capacitance Cg1. For the selected Vg1, the secondgate capacitance Cg2 provided by the MOSFET may be determined using thefollowing formula:

Cg2=Cox/{1+[2×Cox ²×(Vg1−ΔVt)/(ε_(si) ×Q×N _(a))]}^(0.5).

By adjusting a value of the gate bias voltage Vg2 applied to the MOSFETand/or a time period that such a voltage is applied to the MOSFET whileoperating in the second mode, a desired ΔVt may be obtained.Consequently, a desired second gate capacitance Cg2 may be obtained. Inthis manner, a capacitance provided by one or more such MOSFETs (andtherefore provided by a circuit comprising one or more such MOSFETs) maybe adjusted (e.g., tuned in for RF circuits and/or increased fordecoupling).

Using the formulas above, for a MOSFET including a dielectric materialhaving an ε_(d)=15 and for N_(a)=5×10¹⁵/cm³, Vg1=0.5 V and Cox=33.19fF/μm², the MOSFET may provide a first capacitance Cg1=0.009×Cox=0.3fF/μm². Alternatively, by decreasing Vg1 to about 0.1 V, the firstcapacitance Cg1 provided by the MOSFET may be increased to about 0.7fF/μm².

By causing the Vt of the MOSFET to change by about 80 mV, the MOSFET mayprovide a second capacitance Cg2 of about 1.44 fF/μm² for a Vg1 of about0.1 V, which is about twice the first capacitance. However, the secondcapacitance Cg2 may be increased by causing a larger ΔVt.

However, a greater disparity between capacitance provided by a MOSFETemployed as a capacitor before and after a threshold voltage change maybe achieved using a gate bias voltage Vg1 of 0 V than other gate biasvoltages. At Vg1=0 V, the MOSFET operates in a flat-band condition. Acapacitance Cg3 provided by the MOSFET while operating in this conditionis the flat-band capacitance C_(fb) and may be determined using thefollowing formula:

1/Cg3=(1/Cox)+{[ε_(si) ×K×T/(Q ² ×N _(a))]^(0.5)/ε_(si)},

where K is Boltzmann's constant which equals to 1.3806505×10⁻²³Joules/Kelvin and T is the absolute temperature in Kelvin and ΔVt isabout 80 mV. For example, using the above formula, at 30° C., a MOSFEThaving an original Vt may provide a flat-band capacitance Cg3 of 1.7fF/μm². After inducing a ΔVt of about 80 mV, when the MOSFET is operatedin the first mode as a capacitor while having the changed Vt, inresponse to the original gate bias voltage of Vg1=0 V, the MOSFET mayprovide a second gate capacitance Cg4, which may be in the accumulationrange of the first curve 102 and may be larger that Vg3 (and Vg2). Thesecond gate capacitance Cg4 in a flat-band condition provided by theMOSFET may be determined using the following formula:

Cg4=Cox/{1+[2×K×T/(Q×|Vg−Ψ _(s)|)]}

Using the above methods, in accordance with embodiments of the presentinvention, one or more such MOSFETs may be employed as capacitors whichmay provide a programmable (e.g., an adjustable or variable) capacitance(e.g., varactors) in a plurality of circuits. For example, adjustablecapacitors may be employed in many applications of analog circuitdesign. As described in detail below, such adjustable capacitors (e.g.,varactors) may be employed to tune a differential LC-tank oscillatorcircuit adapted to provide a proper frequency (e.g., a proper centerfrequency) when operating in a phase-locked loop (PLL). For example,FIG. 2 is a block diagram of a PLL 200 including a programmablecapacitor in accordance with an embodiment of the present invention.With reference to FIG. 2, the PLL 200 may be similar to a conventionalPLL. However, in contrast to the conventional PLL, one or morecomponents of the PLL 200 may include transistors including a dielectricmaterial having a dielectric constant of about 3.9 to about 25 ascapacitors which may provide a programmable capacitance in the mannerdescribed above. Further, in contrast to a conventional PLL, asdescribed below, the PLL 200 may include a multiplexer adapted toreceive a control signal output from a state machine, and a programmingvoltage that may be employed to adjust a Vt of such a transistor. Themultiplexer may selectively output the programming voltage to thetransistor based on the control signal.

For example, the PLL 200 may include a prescalar M circuit (e.g., logic)202 coupled to a phase frequency detector circuit 204. The prescalar Mcircuit 202 may be adapted to receive a signal fref as input and outputa signal having a frequency 1/M times that of fref therefrom. Such asignal output from the prescalar M circuit 202 may serve as a firstsignal, which may be a known reference signal, and may be input by thephase frequency detector circuit 204. The phase frequency detectorcircuit 204 may be coupled a filter 206 and a lock detection circuit 208adapted to determine whether the PLL 200 has locked and output a signalaccordingly. More specifically, one or more signals output by the phasefrequency circuit 204 may be input by the filter 206 and a lockdetection circuit 208. Similarly, the filter 206 may be coupled to acontrol voltage buffer circuit 210 and a voltage comparator 212 adaptedto determine whether the control voltage of the PLL 200 is greater thanor equal to a predetermined value (e.g., 0 V). More specifically, one ormore signals output by the filter 206 may be input by the controlvoltage buffer circuit 210 and the voltage comparator 212.

The lock detection circuit 208 and the voltage comparator 212 may becoupled to a state machine 214. More specifically, a signal output bythe lock detection circuit 208 and/or a signal output by the voltagecomparator 212 may be input by the state machine 214. Further, the statemachine 214 may also receive a signal including programming control bitsas input. The state machine 214 may output a control voltage selectionbit based on the signal output by the lock detection circuit 208 and thesignal output by the voltage comparator 212. For example, the statemachine 214 may output the program control bits if the signal output bythe lock detection circuit 208 indicates the PLL 200 has locked afrequency and the voltage comparator outputs a signal indicating thecontrol voltage of the PLL 200 is not greater than or equal to thepredetermined value. Further, the state machine 214 and control voltagebuffer circuit 210 may be coupled to an analog multiplexer 216. Morespecifically, a signal (e.g., the control voltage of the PLL 200) outputby the control voltage buffer circuit 210 or a signal (e.g., the programcontrol bits) output by the state machine 214 may be input by the analogmultiplexer 216. Further, the analog multiplexer 216 may receive aprogramming voltage signal as input. The analog multiplexer 216 mayselectively output a signal input by the multiplexer 216 based on thesignal output by the state machine, which may serve as a control signalof the multiplexer 216. The analog multiplexer 216 may be coupled to avoltage-controlled oscillator (VCO) 218 in accordance with an embodimentof the present invention. More specifically, one or more signals outputby the analog multiplexer 216 may input by the VCO 218. Such signals maybe a control voltage and/or a programming voltage. The VCO 218 may becoupled to a divider N circuit 220. More specifically, a signal outputby the VCO 218 may be input by the divider N circuit 220. The divider Ncircuit 220 may divide a frequency of the signal input by the circuit220 (received from the VCO 218) to create and output a second signalhaving a frequency 1/N times that of the signal input by the circuit220. The divider N circuit 220 may be coupled to the phase frequencydetector circuit 204. More specifically, the second signal output by thedivider N circuit 220 may be input by the phase frequency detector 204.

Similar to a conventional PLL, the PLL 200 is adapted to adjust (e.g.,continuously) a frequency and phase of the second signal until thefrequency and phase of the second signal matches the frequency and phaseof the first signal. The signal output by the VCO 218 may serve as anoutput fout, which equals fref times N/M, of the PLL 200 when thefrequency and phase of the second signal matches the frequency and phaseof the first signal, where N and M are integers which typically rangefrom 1 to 1024 but may take on other values as well. Structure andfunction of the prescalar M circuit 202, phase frequency detectorcircuit 204, filter 206, lock detection circuit 208, control voltagebuffer circuit 210, voltage comparator 212 and divider N circuit 220 maybe the same as corresponding circuit of a conventional PLL. Therefore,such circuitry 202-212, 220 is not described in further detail herein.

A VCO of a conventional PLL may be adapted to output a signal having afrequency based on (e.g., proportional to) a control signal (e.g.,voltage) input by the VCO. The VCO may include one or more conventionalcapacitors, and the control voltage input by the VCO may modify acapacitance in the VCO which affects the frequency of the VCO outputsignal. However, during operation of the conventional PLL, the controlvoltage may be limited (e.g., to a value). Therefore, a capacitance inthe VCO by the control voltage may be limited, and a frequency of theVCO output signal may be limited. Further, such limitations may be duein part to random variations in processing and difficult to predictduring the design of the VCO. Consequently, due to such inflexibility ofthe conventional PLL, the control voltage may be insufficient to enablethe VCO to output a signal having a frequency and phase such that theconventional PLL may create a second signal having a frequency and phasethat matches that of a first signal (e.g., a reference signal).

In contrast to the VCO of a conventional PLL, the VCO 218 may includeone or more of the varactors 222 described above (e.g., varactorsincluding dielectric material having a k of about 3.9 to about 25).Further, the VCO 218 may be adapted to receive a control voltage signalor a programming voltage signal. During operation of the PLL 200, thecontrol voltage signal may be applied to the VCO 218. More specifically,the control voltage signal may be applied to at least one of thevaractors 222 such that a first capacitance is created in the VCO 218which may affect a frequency of the VCO output signal, and therefore,affects a frequency and phase of the second signal generated by the PLL200 that should match the frequency and phase of the first signal.

If the PLL 200 is unable to lock the frequency and phase of the secondsignal to the first signal using the control voltage, the programmingvoltage signal may be applied to the VCO 218. More specifically, theprogramming voltage signal may be applied to at least one of thevaractors 222 such that respective Vts of such varactors change (e.g.,from an original Vt to a changed Vt) in the manner described above).Consequently, thereafter, when the control voltage signal is applied toat least one of the varactors 222, a second different (e.g., larger)capacitance is created by the VCO 218. The second capacitance may affectthe frequency of the VCO output signal, and therefore, may affect afrequency of the second signal generated by the PLL 200 such that thePLL 200 may lock the frequency and phase of the second signal to thefrequency and phase of the first signal. In this manner, the samecontrol voltage, which was insufficient to lock the frequency and phaseof the second signal to the frequency and phase of the first signalbefore programming (e.g., causing a Vt change in) at least one varactor222, may be applied to at least one programmed varactor 222 tosuccessfully lock the frequency and phase of the second signal to thefrequency and phase of the first signal. In this manner, the PLL 200provides greater independence of random variations in capacitance due toprocessing than a conventional PLL.

The VCO 218 in accordance with embodiments of the present methods andapparatus may have a plurality of configurations. Exemplary circuitswhich may serve as the VCO 218 are described below with reference toFIGS. 3 and 4 which are block diagrams of first and second exemplaryvoltage-controlled oscillators (VCO) 300, 400, respectively, included inthe PLL 200 in accordance with an embodiment of the present invention.With reference to FIG. 3, the VCO 300 may include a first inductor 302having a first input 304 coupled to a power supply such as V_(DD). Asecond input 306 of the first inductor 302 may be coupled to a varactor222 and a first MOSFET (e.g., NFET) 308. More specifically, the secondinput 306 of the first inductor 302 may be coupled to a first terminal310 of the varactor 222 and a drain or source terminal 312 of the firstNFET 308. A source or drain terminal 314 of the first NFET 308 may becoupled to a power supply such as ground. Although varactor 222 is shownas a single varactor, in some embodiments, varactor 222 may comprise twodiscrete series varactors with the control voltage connected to thecommon point between such varactors.

Similarly, the VCO 300 may include a second inductor 316 having a firstinput 318 coupled to a power supply such as V_(DD). A second input 320of the second inductor 316 may be coupled to the varactor 222 and asecond MOSFET (e.g., NFET) 322. More specifically, the second input 320of the second inductor 316 may be coupled to a second terminal 324 ofthe varactor 222 and a drain or source terminal 326 of the second NFET322. A source or drain terminal 328 of the second NFET 322 may becoupled to a circuit power supply such as ground. Further, a gate 330 ofthe first NFET 308 may be coupled to the second input 320 of the secondinductor 316 and the drain or source terminal 326 of the second NFET332. Similarly, a gate 332 of the second NFET 322 may be coupled to thesecond input 306 of the first inductor 302 and the drain or sourceterminal 312 of the first NFET 308. Inductor inputs 306, 320 or thepotential between them may serve as an output of the first exemplary VCO300.

Further, the first exemplary VCO 300 may be coupled to varactor controlcircuitry 336 adapted to operate the varactor 222 in a first mode toprovide a capacitance and a second mode to change a threshold voltage ofthe varactor 222 from an original threshold voltage to a changedthreshold voltage such that the changed threshold voltage affects acapacitance provided by the varactor 222 when operated in the firstmode. For example, the varactor control circuitry 336 may be or includea multiplexer 338. The control voltage of the PLL 200 may be applied tothe first input 340 of the multiplexer 338. As described above, thecontrol voltage may be employed to lock the frequency and phase of thesecond signal to the frequency and phase of the first signal. Further, aprogramming voltage may be applied to a second input 342 of themultiplexer 338. The programming voltage may be employed to change a Vtof the varactor 222 (e.g., from an original Vt to a changed Vt). Anoutput 344 of the multiplexer 338 may be coupled to a gate terminal 346of the varactor 222. Additionally, the multiplexer 338 may include athird input 348 adapted to receive a multiplexer control signal. Themultiplexer 338 is adapted to selectively output the control voltage orthe programming voltage to the gate terminal 346 of the varactor 222based on the multiplexer control signal. For example, the analogmultiplexer 216 may serve as one or more portions of the varactorcontrol circuitry 336. In such embodiments, the control voltage outputby the control voltage buffer circuit 210 may be applied on the firstinput 340, the programming voltage may be applied on the second input342 and the signal output by the state machine 214 may be input on thethird input 348. The configuration of the VCO 300 is exemplary, andtherefore, the VCO 300 may include a different circuitry adapted tofunction as described below.

During operation of the PLL 300 to lock the frequency and phase of thesecond signal to the frequency and phase of the first signal, thevaractor control circuitry 336 may apply the control voltage to the gateterminal 346 of the varactor 222. Alternatively, the varactor controlcircuitry 336 may apply the programming voltage to the gate terminal 346of the varactor 222 to program the varactor 222. Application of theprogramming voltage may not be allowed to happen during PLL operation.Rather, the programming voltage may be applied during a separatecalibration or adjustment phase in which the PLL is not functioning as aloop. For example, assuming the Vt of the varactor 222 is the originalVt, if the first exemplary VCO 300 is unable to lock the frequency andphase of the second signal to (e.g., within a predetermined distancefrom) the frequency and phase of the first signal using the controlvoltage, the varactor control circuitry 336 may be employed to programthe varactor 222. Thereafter, the varactor control circuitry 336 may beemployed to apply the control voltage to the gate terminal 346 of theprogrammed varactor 222 such that the PLL 300 may lock the frequency andphase of the second signal to the frequency and phase of the firstsignal using the control voltage.

Exemplary design and use of a varactor 222 including a dielectricmaterial having a dielectric constant of about 3.9 to about 25 in a PLL200 (e.g., in a VCO 218, 300 of the PLL 200) is described below. Forexample, during circuit design, a varactor 222 may be designed for theVCO 218, 300 such that a capacitance provided thereby is always belowthe desired minimum value given all process variation effects. Duringcircuit testing, the PLL 200, which includes the varactor 222, prescalarM circuit 202 and divider N circuit 220 which may be used in a final PLLdesign, is locked to a reference frequency in a manner similar to thatduring normal operation of the PLL 200. Because the varactor 222 may bedesigned to be too small, a frequency generated by the VCO 218 may betoo high, and therefore, a sign of the control voltage applied to theVCO 218 may be negative to compensate (e.g., assuming a differentialcontrol voltage signal). Thereafter, a programming voltage may beapplied to the varactor 222 (e.g., via a multiplexer 216, 338) to changethe Vt of varactor 222, and therefore, change a capacitance providedthereby. A programming voltage amplitude and a time period (controlledby program control bits) that such a programming voltage is applied tothe varactor may be adjusted such that a desired change in capacitance(e.g., about less than a 1% capacitance change) may be achieved whichmay enable the PLL to continue to lock. The steps of locking the PLL toa reference frequency and applying a programming voltage to the varactormay be repeated as necessary until a sign of the control voltage isobserved to change. At this point the varactor capacitance has beenadjusted to set the oscillator to the desired center frequency.

FIG. 4 is a block diagram of a second exemplary VCO 400 included in amodified version of the PLL 200 in accordance with an embodiment of thepresent invention. In the modified version of the PLL 200, rather thancoupling to the analog multiplexer 216, the output of the controlvoltage buffer circuit 210 may be coupled to and input by the VCO 218.Further, in addition to the programming voltage, the analog multiplexer216 may receive a functional voltage as input. With reference to FIG. 4,the VCO 400 may include a first inductor 402 having a first input 404coupled to a power supply such as V_(DD). A second input 406 of thefirst inductor 402 may be coupled to a first varactor 408, a secondvaractor 410 and a first MOSFET (e.g., NFET) 412. The second varactor410 may be similar to varactors described above (e.g., varactorsincluding a dielectric material having a k of about 3.9 to about 25).Additionally, in some embodiments, the first varactor 408 may also besimilar to varactors described above. More specifically, the secondinput 406 of the first inductor 402 may be coupled to a first terminal414 of the first varactor 408, a first terminal 416 of the secondvaractor 410 and a drain or source terminal 418 of the first NFET 412. Asource or drain terminal 420 of the first NFET 412 may be coupled to apower supply such as ground.

Similarly, the VCO 400 may include a second inductor 422 having a firstinput 424 coupled to a power supply such as V_(DD). A second input 426of the second inductor 422 may be coupled to the first varactor 408,second varactor 410 and a second MOSFET (e.g., NFET) 428. Morespecifically, the second input 426 of the second inductor 422 may becoupled to a second terminal 430 of the first varactor 408, a secondterminal 432 of the second varactor 410 and a drain or source terminal434 of the second NFET 428. A source or drain terminal 436 of the secondNFET 428 may be coupled to a power supply such as ground. Further, agate 438 of the first NFET 412 may be coupled to the second input 426 ofthe second inductor 422, the second input 430 of the first varactor 408,the second input 432 of the second varactor 410 and the drain or sourceterminal 434 of the second NFET 428. Similarly, a gate 440 of the secondNFET 428 may be coupled to the second input 406 of the first inductor402, the first input 414 of the first varactor 408, the first input 416of the second varactor 410 and the drain or source terminal 418 of thefirst NFET 412. Inductor inputs 406, 426, or the potential between themmay serve as an output of the second exemplary VCO 400.

A gate terminal 444 of the first varactor 408 may be coupled to thecontrol voltage signal of the modified version of the PLL 200. Further,the second exemplary VCO 400 may be coupled to varactor controlcircuitry 446 adapted to operate the second varactor 410 in a first modeto provide a capacitance and a second mode to change a threshold voltageof the second varactor 410 from an original threshold voltage to achanged threshold voltage such that the changed threshold voltageaffects a capacitance provided by the second varactor 410 when operatedin the first mode. For example, the varactor control circuitry 446 maybe or include a multiplexer 448. A functional voltage of the modifiedversion of the PLL 200 may be applied to the first input 450 of themultiplexer 448. The functional voltage may be a DC voltage whose valuemay be appropriate for the loop and may be distinct from the controlvoltage. The functional voltage may be employed to lock the frequencyand phase of the second signal to the frequency and phase of the firstsignal. Further, a programming voltage may be applied to a second input452 of the multiplexer 448. The programming voltage may be employed tochange a Vt of the second varactor 410 (e.g., from an original Vt to achanged Vt). An output 454 of the multiplexer 448 may be coupled to agate terminal 456 of the second varactor 410. Additionally, themultiplexer 448 may include a third input 458 adapted to receive amultiplexer control signal. For example, the analog multiplexer 216 ofthe modified version of the PLL 200 may serve as one or more portions ofthe varactor control circuitry 446. In such embodiments, the functionalvoltage may be applied on the first input 450, the programming voltagemay be applied on the second input 452 and the signal output by thestate machine (e.g., the control voltage selection bit) may be input onthe third input 348. The multiplexer 448 is adapted to selectivelyoutput the functional voltage or the programming voltage to the gateterminal 456 of the second varactor 410 based on the multiplexer controlsignal.

During operation of the modified version of the PLL 200 to lock thefrequency and phase of the second signal to the frequency and phase ofthe first signal, the first varactor 408 may serve as a tuning varactorand the second varactor 410 may serve to set a center frequency of theVCO 400. For example, the control voltage may be applied to the firstvaractor 408 such that the first varactor 408 provides a firstcapacitance. Further, the varactor control circuitry 446 may apply thefunctional voltage to the gate terminal 456 of the second varactor 410such that the second varactor 410 provides a second capacitance, whichmay be the same as or different than the first capacitance. An overallcapacitance created in the VCO 400 may be based on the first and secondcapacitances. The overall capacitance may affect a frequency of the VCOoutput signal, and therefore, may affect a frequency and phase of thesecond signal generated by the modified version of the PLL 200 thatshould match the frequency and phase of the first signal.

Alternatively, the varactor control circuitry 446 may apply theprogramming voltage to the gate terminal 456 of the second varactor 410to program the second varactor 410. For example, assuming the Vt of thesecond varactor 410 is the original Vt, if the second exemplary VCO 400is unable to lock the frequency and phase of the second signal to thefrequency and phase of the first signal using the control and functionalvoltages, the varactor control circuitry 446 may be employed to programthe second varactor 410. Thereafter, the control voltage may be appliedto the gate terminal 444 of the first varactor 408 and the varactorcontrol circuitry 446 may be employed to apply the functional voltage tothe gate terminal 456 of the programmed second varactor 410 such thatthe modified version of the PLL 200 may lock the frequency and phase ofthe second signal to the frequency and phase of the first signal.

The configuration of the VCO 400 is exemplary, and therefore, the VCO400 may include a larger or smaller amount of and/or different circuitryadapted to function as described below. For example, instead of a singletuning varactor 408, a larger number of tuning varactors may beemployed. Additionally or alternatively, instead of a single centerfrequency varactor 410, the second exemplary VCO 400 may include adifferent number of center frequency varactors.

The VCO 400 may include a plurality of varactors (e.g., an array ofvaractors). A subset of the plurality of varactors may receive aprogramming voltage adapted to change capacitances provided thereby,respectively. By configuring the VCO 400 such that only a subset of aplurality of varactors included therein may receive the programmingvoltage, in some embodiments, the analog multiplexer 216 may be replacedby a programmable level driver (PLD) assuming a functional voltageprovided to the subset may be set to a static voltage during functionaloperation of the modified version of the PLL 200.

Additionally, adjustable capacitors may be employed in a different typeof circuit. For example, FIG. 5 is a block diagram of a capacitor array500 including at least one programmable capacitor in accordance with anembodiment of the present invention. With reference to FIG. 5, thecapacitor array 500 may include a plurality of programmable capacitorsets. Each set may include one or more programmable capacitors includinga dielectric material having a k of about 3.9 to about 25. For example,the capacitor array 500 may include a first programmable capacitor set502 coupled across first and second functional terminals 504, 506 of thecapacitor array 500. The functional terminals 504, 506 may serve as anoutput of the capacitor array 500. Further, the capacitor array 500 mayinclude a second programmable capacitor set 508 coupled in parallel withthe first programmable capacitor 502, a third programmable capacitor set510 coupled in parallel with the first and second programmable capacitorsets 502, 508 and so on to an nth programmable capacitor set 512 coupledin parallel with the other sets 502, 508, 510.

The first programmable capacitor set 502 may include a firstprogrammable capacitor 514 having a dielectric material having a k ofabout 3.9 to about 25. A first input 516 of the first programmablecapacitor 514 may be coupled to the first functional terminal 504. Asecond input 518 of the first programmable capacitor 514 (e.g., a gateterminal thereof) may be coupled to the second functional terminal 506via a first switch 520 of the set 502. Operation of the first switch 520is based on a control signal Control Bit 0 input by a control input 522of the first switch 520. For example, the first switch 520 may closewhen Control Bit 0 is asserted. Additionally, the second input of thefirst programmable capacitor 518 may be coupled to a programmingterminal (represented as “Fine Adjust Voltage Terminal” in FIG. 5) 524via a second switch 526 of the first set 502. Operation of the secondswitch 526 is based on a control signal (represented as “Fine Adjust 0”in FIG. 5) input by a control input 528 of the second switch 526. Forexample, the second switch 526 may close when Fine Adjust 0 is asserted.In operation, for example, the first switch 520 may be closed byasserting Control Bit 0. Therefore, an overall capacitance of thecapacitor array 500 may be based at least on the programmable capacitor514 in the first set 502. Alternatively, the second switch 526 may beclosed by asserting Fine Adjust 0. Consequently, a signal (e.g.,voltage) asserted on the programming terminal may be applied to the gateterminal 518 of the first programmable capacitor 514 such that a Vt ofthe programmable capacitor 514 may change (e.g., from an original Vt toa changed Vt). In this manner, a capacitance subsequently provided bythe programmable capacitor 514, and therefore, the first set 502 may beadjusted.

The second programmable capacitor set 508 may include first and secondprogrammable capacitors 530, 532 having a dielectric material having a kof about 3.9 to about 25. Respective first inputs 534, 536 of the firstand second programmable capacitors 530, 532 may be coupled to the firstfunctional terminal 504. Respective second inputs 538, 540 of the firstand second programmable capacitors 530, 532 (e.g., gate terminalsthereof) may be coupled to the second functional terminal 506 via afirst switch 542 of the set 508. Operation of the first switch 542 isbased on a control signal Control Bit 1 input by a control input 544 ofthe first switch 542. For example, the first switch 542 may close whenControl Bit 1 is asserted. Additionally, the respective second inputs538, 540 of the first and second programmable capacitors 530, 532 may becoupled to the programming terminal 524 via a second switch 546 of thesecond set 508. Operation of the second switch 546 is based on a controlsignal (represented as “Fine Adjust 1” in FIG. 5) input by a controlinput 548 of the second switch 546. For example, the second switch 546may close when Fine Adjust 1 is asserted. In operation, for example, thefirst switch 542 may be closed by asserting Control Bit 1. Therefore, anoverall capacitance of the capacitor array 500 may be based at least onthe programmable capacitors 530, 532 in the second set 508.Alternatively, the second switch 546 may be closed by asserting FineAdjust 1. Consequently, a signal (e.g., voltage) asserted on theprogramming terminal may be applied to respective gate terminals 538,540 of the first and second programmable capacitors 530, 532 such that aVt of each such programmable capacitors 530, 532 may change (e.g., froman original Vt to a changed Vt). In this manner, a capacitancesubsequently provided by the first and second programmable capacitors530, 532, and therefore, the second set 508 may be adjusted.

The third programmable capacitor set 510 may include first throughfourth programmable capacitors 550-556 having a dielectric materialhaving a k of about 3.9 to about 25. Respective first inputs 558-564 ofthe first through fourth programmable capacitors 550-556 may be coupledto the first functional terminal 504. Respective second inputs 566-572of the first through fourth programmable capacitors 550-556 (e.g., gateterminals thereof) may be coupled to the second functional terminal 506via a first switch 574 of the set 510. Operation of the first switch 574is based on a control signal Control Bit 2 input by a control input 576of the first switch 574. For example, the first switch 574 may closewhen Control Bit 2 is asserted. Additionally, the respective secondinputs 566-572 of the first through fourth programmable capacitors550-556 may be coupled to the programming terminal 524 via a secondswitch 578 of the third set 510. Operation of the second switch 578 isbased on a control signal (represented as “Fine Adjust 2” in FIG. 5)input by a control input 580 of the second switch 578. For example, thesecond switch 578 may close when Fine Adjust 2 is asserted. Inoperation, for example, the first switch 574 may be closed by assertingControl Bit 2. Therefore, an overall capacitance of the capacitor array500 may be based at least on the programmable capacitors 550-556 in thethird set 510. Alternatively, the second switch 578 may be closed byasserting Fine Adjust 2. Consequently, a signal (e.g., voltage) assertedon the programming terminal is applied to respective gate terminals566-572 of the first through fourth programmable capacitors 550-556 suchthat a Vt of each such programmable capacitor 550-556 may change (e.g.,from an original Vt to a changed Vt). In this manner, a capacitancesubsequently provided by the first through fourth programmablecapacitors 550-556, and therefore, the third set 510 may be adjusted.

The nth programmable capacitor set 512 may include 2^(n) programmablecapacitors 582, 584 (only two shown) having a dielectric material havinga k of about 3.9 to about 25. Respective first inputs 586, 588 of thefirst through 2^(n)th programmable capacitors 582, 584 may be coupled tothe first functional terminal 504. Respective second inputs 590, 592 ofthe first through 2^(n)th programmable capacitors 582, 584 (e.g., gateterminals thereof) may be coupled to the second functional terminal 506via a first switch 594 of the nth set 512. Operation of the first switch594 is based on a control signal Control Bit n input by a control input596 of the first switch 594. For example, the first switch 594 may closewhen Control Bit n is asserted. Additionally, the respective secondinputs 590-592 of the first through 2^(n)th programmable capacitors 582,584 may be coupled to the programming terminal 524 via a second switch598 of the nth set 512. Operation of the second switch 598 is based on acontrol signal (represented as “Fine Adjust n” in FIG. 5) input by acontrol input 600 of the second switch 598. For example, the secondswitch 598 may close when Fine Adjust n is asserted. In operation, forexample, the first switch 594 may be closed by asserting Control Bit n.Therefore, an overall capacitance of the capacitor array 500 may bebased at least on the programmable capacitors 582-584 in the nth set512. Alternatively, the second switch 598 may be closed by assertingFine Adjust n. Consequently, a signal (e.g., voltage) asserted on theprogramming terminal is applied to respective gate terminals 590, 592 ofthe first through nth programmable capacitors 582, 584 such that a Vt ofeach such programmable capacitors 582, 584 may change (e.g., from anoriginal Vt to a changed Vt). In this manner, a capacitance subsequentlyprovided by the first through nth programmable capacitors 582, 584, andtherefore, the nth set 512 may be adjusted.

Therefore, the control signals Control Bit 0-Control Bit n may beemployed to adjust (e.g., tune) an overall capacitance of the capacitorarray 500. For example, by asserting one or more control signals ControlBit 0-Control Bit n, an overall capacitance of the capacitor array 500may be adjusted to be based on programmable capacitors included in sets502, 508, 510, 512 corresponding to such asserted control signals. Inthis manner, the capacitor array 500 is a binary weighted array ofcapacitors (e.g., programmable capacitors as described above). Binaryselection of the control bits Control Bit 0-Control Bit n may serve toprovide a coarse adjustment to the overall capacitance provided by thecapacitor array 500 (e.g., provided between the first and secondfunctional terminals 504, 506). Further, an overall capacitance 500provided by the capacitor array 500 may be adjusted (e.g., fine tuned)by changing a Vt of (e.g., programming) one or more programmablecapacitors 514, 530-532, 550-556, 582-584 of the capacitor array 500,and thereafter, asserting a control bit corresponding thereto such thatthe overall capacitance of the capacitor array 500 may be based on suchprogrammed capacitors. Although the second switches 526, 546, 578, 598of the programmable capacitor sets 502, 508, 510, 512 are coupled todifferent control signals Fine Adjust 0, Fine Adjust 1, Fine Adjust 2,Fine Adjust n, in some embodiments, such switches 526, 546, 578, 598 maybe coupled to the same control signal, and therefore, all programmablecapacitors 514, 530-532, 550-556, 582-584 are programmed at the sametime.

As described above, control signals Control Bit 0-Control Bit n serve toprovide a coarse adjustment (e.g., an initial adjustment) and controlsignals Fine Adjust 0-Fine Adjust n serve to provide a fine adjustmentto the overall capacitance provided by the capacitor array 500. However,in some embodiments, control signals Fine Adjust 0-Fine Adjust n mayserve to provide a coarse adjustment and control signals Control Bit0-Control Bit n may serve to provide a fine adjustment to the overallcapacitance provided by the capacitor array 500. In this manner, anoverall capacitance of the capacitor array 500 may be tuned. A size of asmallest unit capacitor (e.g., programmable capacitor) in the capacitorarray and a capacitance range that may be created by programming theprogrammable capacitors 514, 530-532, 550-556, 582-584 may determinewhether control signals Control Bit 0-Control Bit n serve to provide thecoarse adjustment (e.g., an initial adjustment) and control signals FineAdjust 0-Fine Adjust n serve to provide the fine adjustment to theoverall capacitance provided by the capacitor array 500 or whethercontrol signals Fine Adjust 0-Fine Adjust n serve to provide the coarseadjustment and control signals Control Bit 0-Control Bit n serve toprovide the fine adjustment to the overall capacitance provided by thecapacitor array 500.

Through use of the present methods and apparatus, varactors having adielectric material including a dielectric constant of about 3.9 toabout 25 may be employed in a variety of circuit designs, such as a PLL200 a binary weighted capacitor array 500, and/or the like, for example.The varactors including a dielectric material having a dielectricconstant of about 3.9 to about 25 may provide a high quality factor(Q-factor) and therefore provide a low-leakage capacitance.Additionally, such varactors provide a wide tuning range. For example,such a varactor may provide a capacitance between about 0.1 fF/μm² toabout 2.0 fF/μm² (although a larger of smaller and/or different tuningrange may be employed). Further, manufacturing of such varactors mayeasily be integrated into existing CMOS processes (e.g., without a needfor additional masks). For example, manufacturing of such varactors maybe integrated into methods of manufacturing standard planar CMOS andfinFET technologies. More specifically, manufacturing of such varactorsmay be integrated into methods of manufacturing silicon-on-insulator(SOI) and finFET semiconductor devices where an active silicon layer isinsulated from a remaining portion of a substrate (e.g., a bulk siliconregion). Due to the high quality factor, a varactor in accordance withembodiments of the present invention, and a circuit (e.g., a varactorarray) comprising such a varactor, may provide a built-in or autonomicmemory capability such that the varactor may retain state (e.g., store acapacitance). Therefore, a circuit including such a varactor may notrequire additional circuitry (e.g., non-volatile memory) to store acapacitance.

The foregoing description discloses only exemplary embodiments of theinvention. Modifications of the above disclosed apparatus and methodswhich fall within the scope of the invention will be readily apparent tothose of ordinary skill in the art. For instance, varactors having adielectric material including a dielectric constant of about 3.9 toabout 25 employed in a circuit described above may be of the same size.Alternatively, two or more of such varactors may have different sizes.

Accordingly, while the present invention has been disclosed inconnection with exemplary embodiments thereof, it should be understoodthat other embodiments may fall within the spirit and scope of theinvention, as defined by the following claims.

1. A semiconductor device having an adjustable capacitance, comprising:a transistor formed on a substrate having: a gate region including adielectric material having a dielectric constant of about 3.9 to about25; wherein the transistor is adapted to operate in a first mode toprovide a capacitance; and wherein the transistor is adapted to operatein a second mode to change a threshold voltage of the transistor from anoriginal threshold voltage to a changed threshold voltage such that thechanged threshold voltage affects a capacitance provided by thetransistor when operated in the first mode.
 2. The semiconductor deviceof claim 1 wherein: the semiconductor device further includes a sourcediffusion region and a drain diffusion region; and the transistor isadapted to operate in the first mode to provide the capacitance when avoltage is applied to the gate region, and the source diffusion region,drain diffusion region and substrate are grounded.
 3. The semiconductordevice of claim 1 wherein the dielectric material is hafnium siliconoxide (HfSiO).
 4. The semiconductor device of claim 1 wherein thetransistor is adapted to provide low-leakage capacitance.
 5. Thesemiconductor device of claim 1 wherein the transistor is furtheradapted to provide a capacitance of about 0.1 fF/μm² to about 2.0fF/μm².
 6. The semiconductor device of claim 1 wherein the transistor isadapted to store a capacitance state.
 7. A system adapted to provide avariable capacitance, comprising: a circuit including at least onetransistor including a dielectric material having a dielectric constantof about 3.9 to about 25; wherein each of the at least one transistor isadapted to operate in a first mode to provide a capacitance; whereineach of the at least one transistor is adapted to operate in a secondmode to change a threshold voltage of the transistor from an originalthreshold voltage to a changed threshold voltage such that the changedthreshold voltage affects a capacitance provided by the transistor whenoperated in the first mode; and wherein a capacitance provided by thecircuit is based on the capacitance provided by each of the at least onetransistor.
 8. The system of claim 7 wherein the circuit is avoltage-controlled oscillator of a phase-locked loop.
 9. The system ofclaim 7 wherein the circuit is a binary weighted array of the at leastone transistor.
 10. The system of claim 7 further comprising controlcircuitry coupled to one or more of the at least one transistor andadapted to: cause one or more of the at least one transistor to operatein the first mode; and cause one or more of the at least one transistorto operate in the second mode.
 11. The system of claim 10 wherein: thecircuit is a voltage-controlled oscillator of a phase-locked loop (PLL);and the control circuitry includes a multiplexer adapted to: selectivelyoutput a functional voltage to the at least one transistor such that theat least one transistor operates in the first mode to provide acapacitance based on the functional voltage; and selectively output aprogramming voltage to the at least one transistor such that the atleast one transistor operates in the second mode to change a thresholdvoltage of the at least one transistor based on the programming voltage.12. The system of claim 11 wherein the functional voltage is the controlvoltage of the PLL.
 13. The system of claim 11 wherein the controlcircuitry is further adapted to: selectively output a functional voltageto the at least one transistor such that the at least one transistoroperates in the first mode to provide a first transistor capacitancebased on the functional voltage such that the circuit provides a firstcircuit capacitance that does not lock the PLL within a predetermineddistance from a center control voltage; selectively output a programmingvoltage to the at least one transistor such that a threshold voltage ofthe at least one transistor changes from an original threshold voltageto a changed threshold voltage such that the changed threshold voltageaffects a capacitance provided by the transistor, and therefore thecircuit, when operated in the first mode; and thereafter, selectivelyoutput the functional voltage to the at least one transistor such thatthe at least one transistor operates in the first mode to provide asecond transistor capacitance based on the functional voltage such thatthe circuit provides a second circuit capacitance that locks the PLL.14. The system of claim 10 wherein: the circuit includes a first set ofone or more of the transistors coupled in parallel to a second set ofone or more of the transistors; and the control circuitry is furtheradapted to: cause transistors in one or more of the first and secondsets to operate in the first mode such that the circuit provides a firstcircuit capacitance; and cause the transistors in one or more of thefirst and second sets to operate in the second mode such that respectivethreshold voltages of the transistors change; and thereafter, cause thetransistors in one or more of the first and second sets to operate inthe first mode such that the circuit provides a second circuitcapacitance.
 15. The system of claim 14 wherein the control circuitryincludes switches adapted to: cause a functional voltage to be appliedto transistors in one or more of the first and second sets such that thetransistors operate in the first mode and the circuit provides a circuitcapacitance; and cause a programming voltage to be applied totransistors in one or more of the first and second sets such that thetransistors operate in the second mode and respective threshold voltagesof the transistors change.